1. Field of the Invention
The present invention relates generally to power converters and circuits, e.g., circuit boards and, more particularly, to circuit board layouts for improving power converter performance.
2. Description of the Related Art
The improvement of power field effect transistor (FET) technologies such as silicon metal oxide semiconductor FETs and the introduction of gallium nitride (GaN) based transistors allow switching power supplies to achieve faster switching speeds by reducing switching related charges and package parasitic inductance. With higher switching speeds and lower package parasitic inductance, the circuit board layout of converter components becomes a limiting factor in converter performance because the layout of components has a significant effect on the overall level of parasitic inductance. An improved circuit board layout is needed to minimize the high frequency loop inductance in a multilayer circuit board design and improve converter performance.
High frequency power loop inductance, controlled by circuit board layout, is a major contributor to loss of power converter efficiency. Consequently, the layout of the devices and high frequency bus capacitors is critical to high frequency performance. To verify the relationship between loop inductance and efficiency loss, different layouts with similar common source inductances and different loop inductances were compared. FIG. 1 is a graph charting the impact of high frequency power loop inductance on power converter efficiency for an eGaN® FET design at 1 MHz. Specifically, as shown in FIG. 1, an increase in the high frequency loop inductance from approximately 0.4 nH to approximately 2.9 nH resulted in a decrease in efficiency by over 4%.
Another impact of the faster switching speeds provided by lower figure of merit devices is an increase in voltage overshoot when compared to devices with slower switching speeds. Decreasing the high frequency loop inductance results in lower voltage overshoot, increased input voltage capability, and reduced electromagnetic interference. FIG. 2A and FIG. 2B depict drain to source voltage waveforms of a synchronous rectifier for designs with high frequency loop inductances of 1.6 nH and 0.4 nH, respectively. As shown in FIGS. 2A and 2B, a decrease in high frequency loop inductance from 1.6 nH (FIG. 2A) to 0.4 nH (FIG. 2B) results in a 75% decrease in voltage overshoot.
Conventionally, two circuit board layouts have been employed to minimize the high frequency loop inductance as described below in connection with FIGS. 3A-3B and 4A-4C. In the first conventional layout design, illustrated in FIGS. 3A and 3B, high frequency bus capacitors and devices are arranged on a top layer of the circuit board. The high frequency power loop for this design is disposed on a top layer of the circuit board and is considered a lateral power loop because the loop flows parallel to the board plane on a single layer. In this design, an inductor connection is created through internal layers by using vias located between a top switch and a synchronous rectifier. A driver is located in close proximity to the eGaN® FETs to minimize and stabilize the common source inductance.
FIGS. 3A and 3B depict the part placement of an eGaN® FET design resulting in a lateral high frequency power loop 302. In this design, capacitors 303 and eGaN® FETs 306, 307 are located on a top layer 305 of a circuit board 310. A power loop current 302 flows through the capacitors 303 and the eGaN® FETs 306, 307. An inductor connection is created through internal layers by using vias 311 extending between the top switch 306 and synchronous rectifier 307. A driver 308 is located in close proximity to the eGaN® FETs 306, 307 to minimize and stabilize the common source inductance.
While minimizing the physical size of the loop is important to reduce parasitic inductance, the design of inner layers is also critical. For the lateral power loop design, illustrated in FIG. 3B, a first inner layer serves as a “shield layer” 309. The shield layer 309 has a critical role to shield the circuit from magnetic fields generated by the high frequency power loop 302. To perform this shielding function, the high frequency power loop 302 generates a magnetic field that induces a current, opposite in direction to the power loop current, within the shield layer 309. The current induced in the shield layer 309 generates a magnetic field of opposite polarity to the magnetic field of the power loop. The magnetic fields created within the shield layer 309 and the power loop 302 neutralize each other translating into a reduction in parasitic inductance.
The lateral power loop design provides advantages and disadvantages. For example, the level of high frequency loop inductance should show little dependence on board thickness since the power loop is located on the top layer 305. The lateral power loop design's lack of dependence on board thickness allows for thicker board design. On the other hand, the level of loop inductance in this design is likely very dependent on the distance from the power loop to the shield layer. This dependence on distance limits the thickness of a top layer 305. The shield layer also contributes additional conductive losses to the power converter, decreasing performance.
In the second conventional layout design illustrated in FIGS. 4A-4C, the high frequency bus capacitors and devices are disposed on opposite sides of a circuit board, with capacitors generally being located directly underneath the devices to minimize physical loop size. This layout creates a vertical power loop because the power loop travels perpendicular to the board plane through vias which complete the power loop through the board.
FIGS. 4A-4C depict an eGaN® FET design resulting in a vertical high frequency power loop 400. In this design, eGaN® FETs 401, 408 are arranged on a top layer 402 of a circuit board 403 and capacitors 404 are arranged on a bottom layer 405 of the circuit board 403. High frequency power loop current 406 flows through the eGaN® FETs 401, 408 located on the top layer 402 of the circuit board 403. The loop current 406 then flows through vias 409 and through the capacitors 404 located on the bottom layer 405 of the circuit board 403. The current 406 then flows back to the eGaN® FETs 401, 408 through vias 410. Space 407 is left between the eGaN® FETs 401, 408 to allow for inductor connection.
The FIGS. 4A-4C eGaN® FET design does not contain a shield layer due to the vertical structure of the power loop. As opposed to the use of a shield plane to reduce loop inductance, the vertical power loop uses a magnetic field self-cancellation method to reduce inductance. For the circuit board layout, the board thickness is generally much thinner than the horizontal length of the power loop paths on the top and bottom side of the board. As the thickness of the board decreases, the area of the vertical power loop shrinks significantly when compared to the lateral power loop, and the current flowing in opposing directions on the top and bottom layers begins to provide magnetic field self-cancellation, further reducing parasitic inductance. Accordingly, the board thickness must be minimized in this design to create an effective vertical power loop.
Like the lateral power loop design illustrated in FIGS. 3A-3B, the vertical power loop design also has advantages and disadvantages. For example, the distance between the first inner layer and top layer has little impact on the loop inductance. Therefore, the thickness of the top layer does not significantly affect the level of loop inductance. On the other hand, the level of loop inductance is heavily dependent on the overall board thickness because the power loop paths are located on the top and bottom layers of the CIRCUIT BOARD.
Accordingly, a semiconductor device layout for minimizing parasitic inductance and improving converter performance is desired.